1. Field of the Invention
The invention pertains generally to the field of electronic graphic systems and more particularly to write-protecting areas or patterns of a bit mapped memory used in these graphic systems.
2. Description of the Prior Art
Graphic systems typically use full field or bit mapped memories configured in an X, Y plane format to hold information for utilization in the generation of a graphic display. These memories are X and Y addressed for entering one bit of data at each addressed point. Data stored in this manner is subsequently displayed on a CRT as an X, Y plane graphic.
A vector generator, directed by a central processing unit (CPU) software, creates a display for entry into the bit map memory. In a real time graphic system speed or execution time is an important factor. This speed may be achieved by using a set of routines each configured to draw different parts of the display. These routines are repeated for each frame of the display system with only the input data altered to reflect dynamic changes. This procedure, however, may cause segments of one routine to be drawn over an area controlled by another routine when the input coordinates are changed. In the prior art this over lapping is eliminated with software having limits set therein which, when exceeded, cause unwanted segments of a routines display to be erased. These prior art remedies, however, require additional execution time, thus adversely affecting the speed of the display system. Some prior write-protect circuits use a PROM mask. These masks require large PROM sizes, extra chips to latch addresses and to multiplex output signals, and exhibit slow access times.
A need exists for a write-protect system capable of detecting when a write operation is inside or outside of a specified area or pattern with sufficient speed to respond within a single write operation.